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freescale semiconductor, inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. document number: mc33897 rev. 18.0, 4/2012 freescale semiconductor technical data ? freescale semiconductor, inc., 2006 - 2012. all rights reserved. single wire can transceiver the 33897 series provides a physical layer for digital communication using a carrier sense multiple access/collision resolution (csma/cr) data link oper ating over a single wire medium. this is more commonly referred to as single-wire controller area network (swcan). the 33897 series operates directly from a vehicle's 12 v battery system or a broad range of dc-power sources. it can operate at low or high (33.33 kbps or 83.33 kbps) data rates. a high-voltage wake-up feature allows the device to control the regulator used in support of the mcu and other logic. the device includes a control pin that can be used to put the module regulator into sleep mode. the presence of a defined wake-up voltage level on the bus will reactivate the control line to turn the regulator and the system back on. the device complies with the gmw3089v2.4 general motors corporation specification. features ? waveshaping for low electrom agnetic interference (emi) ? detects and automatically handles loss of ground ? worst-case sleep mode current of only 60 a ? current limit prevents damage due to bus shorts ? built-in thermal shutdown on bus output ? protected against vehicular electrical transients ? under-voltage lockout prevent s false data with low battery figure 1. 33897 simplified application diagram single-wire can transceiver 33897 ef (pb-free) suffix 98asb42565b 14-pin soicn ordering information device temperature range (t a ) package mcz33897tef/r2 -40 to 125 c 14 soicn *mc33897ctef/r2 *recommended device for all new designs vbatt 4 mode 1 mode 0 rxd txd gnd load cntl bus mcu battery voltage en power source regulator v cc swc bus 33897
analog integrated circuit device data 2 freescale semiconductor 33897 device variations device variations *recommended device for all new designs table 1. device variations part no. load voltage sleep mode see page 33897t 1.0 v max 7 *33897ct 0.1 v max 7
analog integrated circuit device data freescale semiconductor 3 33897 internal block diagram internal block diagram figure 2. 33897 simplifi ed internal block diagram co ntrol mode0 mode1 tx bus drvr bu s rcvr load sw itch wa ve sha pin g e n hvwu en tx data txd hv w u de t rxd rx data tim ers timer osc un der vo ltag e detect load bat cnt l gnd bus disable disable mode vbatt txd bus drvr bus rcvr hvwu enable waveshaping enable txd data disable hvwu detect rxd data mode control cntl disable
analog integrated circuit device data 4 freescale semiconductor 33897 pin connections pin connections figure 3. 33897 pin connections table 2. pin definitions a functional description of each pin can be found in the functional pin description section, beginning on page 12 . 33897 pin pin name formal name definition 1, 7, 8, 14 gnd ground electrical common ground and heat removal. a good thermal path will also reduce the die temperature. 2 txd transmit data data input here will appear on the bus pin. a logic [0] will assert the bus, a logic [1] will make the bus go to the recessive state. 3, 4 mode0, mode1 mode control these pins control sleep mode, transmit level, and speed. they have weak pull- downs. 5 rxd receive data open drain output of the data on bus. a recessive bus = a logic [1], a dominant bus = logic [0]. an external pull-up is required. 6, 13 nc no connect no internal connection to these pins. pin 13 can be connected to gnd. 9 cntl control provides a battery level logic signal. 10 vbatt battery power input. an external diode is needed for reverse battery protection. 11 load load the external bus load resistor connects here to prevent bus pull-up in the event of loss of module ground. 12 bus bus this pin connects to the bus through external components. gnd vbatt cntl gnd nc bus load gnd rxd nc gnd txd mode0 mode1 5 6 7 2 3 4 14 10 9 8 13 12 11 1 33897
analog integrated circuit device data freescale semiconductor 5 33897 electrical characteristics maximum ratings electrical characteristics maximum ratings table 3. maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value unit electrical ratings supply voltage v batt - 0.3 to 40 v input logic voltage v in - 0.3 to 7.0 v rxd pin voltage v rxd - 0.3 to 7.0 v cntl pin voltage v cntl - 0.3 to 40 v esd voltage (1) human body model all pins except bus bus pin machine model v esd 2000 4000 100 v thermal ratings ambient operating temperature (1) t a - 40 to 125 c junction operating temperature t j - 40 to 150 c storage temperature t stg - 55 to 150 c junction-to-ambient thermal resistance r ja 150 c/w peak package reflow temperature during reflow (2) , (3) t pprt note 3. c notes 1. esd testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ), machine model (c zap = 200 pf, r zap = 0 ). 2. pin soldering temperature limit is for 10 seconds maximum duration. not designed for immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 3. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freesca le.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. (i .e. mc33xxxd enter 33xxx), and review parametrics.
analog integrated circuit device data 6 freescale semiconductor 33897 electrical characteristics static electrical characteristics static electrical characteristics table 4. static electric al characteristics characteristics noted under conditions of -40 c t a 125 c, unless otherwise stated. voltages are relative to gnd, unless otherwise noted. all positive currents are into t he pin. all negative curr ents are out of the pin. characteristic symbol min typ max unit general quiescent current sleep 5.0 v v batt 13 v (4) awake with transmitter disabled 5.0 v v batt 26.5 v awake with transmitter enabled 5.0 v v batt 26.5 v i qslp i qatdis i qaten ? ? ? 45 ? ? 60 4.0 9.0 a ma ma under-voltage shutdown v battuv 4.0 ? 5.0 v under-voltage hysteresis v uvhys 0.1 ? 0.5 v thermal shutdown (5) 5.0 v v batt 26.5 v t sd 150 ? 190 c thermal shutdown hysteresis (5) 5.0 v v batt 26.5 v t sdhys 10 ? 20 c logic i /o, mode0, mode1, txd, rxd logic input low level (mode0, mode1, and txd) 5.0 v v batt 26.5 v v il ? ? 0.8 v logic input high level (mode0, mode1, and txd) 5.0 v v batt 26.5 v v ih 2.0 ? ? v mode pin pull-down current (mode0 and mode1) pin voltage = 0.8 v, 5.0 v v batt 26.5 v i pd 10 ? 50 a receiver output low (rxd) i in = 2.0 ma, 5.0 v v batt 26.5 v v ol ? ? 0.45 v cntl cntl output low i in = 5.0 a, 5.0 v v batt 26.5 v v olcntl ? ? 0.8 v cntl output high i out = 180 a, 5.0 v v batt 26.5 v v ohcntl v batt - 0.8 ? v batt v notes 4. after t cntlfdly 5. thermal shutdown causes the bus output driver to be disabled. guaranteed by characterization.
analog integrated circuit device data freescale semiconductor 7 33897 electrical characteristics static electrical characteristics load load voltage rise (6) normal speed and voltage mode, transmit high- voltage mode, transmit high speed mode i in = 1.0 ma, 5.0 v v batt 26.5 v sleep mode i in = 7.0 ma 33897t i in = 7.0 ma (7) 33897ct loss of battery i in = 7.0 ma v ldrise ? ? ? ? ? ? ? ? 0.1 1.0 0.1 1.0 v load leakage during loss of module ground (8) 0.0 v v batt 18 v 33897t 0.0 v v batt 18 v 33897ct i ldleak 0.0 -10 ? ? - 90 10 a bus passive out bus leakage passive in 0.0 v v batt 26.5 v, -1.5 v v bus < 0 v active in 0.0 v v batt 26.5 v, 0 v < v bus 12.5 v bus leakage during loss of module ground (9) 0.0 v v batt 18 v 33897t 0.0 v v batt 18 v 33897ct i leak i lkai i blklog -5.0 -5.0 -10 0.0 ? ? ? ? 5.0 5.0 10 -90 a high voltage wake-up mode output high voltage 12 v v batt 26.5 v, 200 r l 3332 33897t 33897ct 5.0 v v batt < 12 v, 200 r l 3332 v hvwuohf v hvwuoho 9.7 9.9 lesser of v bat - 1.5 or 9.7 ? ? ? 12.5 12.5 v batt v high speed mode output high voltage 8.0 v v batt 16 v, 75 r l 135 v ohhs 4.2 ? 5.1 v normal mode output high voltage 6.0 v v batt 26.5 v, 200 r l 3332 5.0 v v batt < 6.0 v, 200 r l 3332 v nohf v noho 4.4 lesser of v batt - 1.6 or 4.4 ? ? 5.1 lesser of v batt or 5.1 v notes 6. gmw3089v2.4 specifies the maximum load voltage rise to be 0.1 v whenever module battery is intact, including when in sleep mode. the maximum load voltage rise of 1.0 v in sleep mode is a gm-approved exception to gmw3089v2.4. 7. 33897ct removes the diode drop during sleep mode. 8. load pin is at system ground voltage. 9. bus pin is at system ground voltage table 4. static electrical characteristics (continued) characteristics noted under conditions of -40 c t a 125 c, unless otherwise stated. voltages are relative to gnd, unless otherwise noted. all positive currents are into t he pin. all negative curr ents are out of the pin. characteristic symbol min typ max unit
analog integrated circuit device data 8 freescale semiconductor 33897 electrical characteristics static electrical characteristics bus (continued) bus low voltage 5.0 v v batt 26.5 v, 200 r l 3332 v ol - 0.2 ? 0.2 v short-circuit bus output current dominant state, 5.0 v v batt 26.5 v i bsc -350 ? - 100 ma input threshold awake 5.0 v v batt 26.5 v sleep 12 v v batt 26.5 v sleep 5.0 v v batt < 12 v v bia v bisf v biso 2.0 6.6 lesser of 6.6 v or v batt - 4.3 ? ? ? 2.2 7.9 lesser of 7.9 v or v batt - 3.25 v table 4. static electrical characteristics (continued) characteristics noted under conditions of -40 c t a 125 c, unless otherwise stated. voltages are relative to gnd, unless otherwise noted. all positive currents are into t he pin. all negative curr ents are out of the pin. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 9 33897 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 5. dynamic electrical characteristics characteristics noted under conditions of -40 c t a 125 c, unless otherwise stated. volt ages are relative to gnd unless otherwise noted. all positive currents are into the pin. all negative currents are out of the pin. characteristic symbol min typ max unit bus normal speed rising output delay 200 r l 3332 , 1.0 s load time constants 4.0 s measured from txd = v il to v bus as follows: max time to v busmod = 3.7 v, 6.0 v v batt 26.5 v (10) min time to v busmod = 1.0 v, 6.0 v v batt 26.5 v (10) max time to v busmod = 2.7 v, v batt = 5.0 v (10) min time to v busmod = 1.0 v, v batt = 5.0 v (10) t dlynormro 2.0 ? 6.3 s normal speed falling output delay 200 r l 3332 , 1.0 s load time constants 4.0 s measured from txd = v ih to v bus as follows: max time to v busmod = 1.0 v, 6.0 v v batt 26.5 v (10) min time to v busmod = 3.7 v, 6.0 v v batt 26.5 v (10) max time to v busmod = 1.0 v, v batt = 5.0 v (10) min time to v busmod = 2.7 v, v batt = 5.0 v (10) t dlynormfo 1.8 ? 8.5 s high speed rising output delay 75 r l 135 , 0.0 s load time constants 1.5 s, 8.0 v v batt 16 v measured from txd = v il to v bus as follows: max time to v bus = 3.7 v (11) min time to v bus = 1.0 v (11) t dlyhsro 0.1 ? 1.7 s high speed falling output delay 75 r l 135 , 0.0 s load time constants 1.5 s, 8.0 v v batt 16 v measured from txd = v ih to v bus as follows: max time to v bus = 1.0 v (11) min time to v bus = 3.7 v (11) t dlyhsfo 0.04 ? 3.0 s notes 10. v busmod is the voltage at the busmod node in figure 6 , page 13 . 11. v bus is the voltage at the bus pin in figure 7 , page 14 .
analog integrated circuit device data 10 freescale semiconductor 33897 electrical characteristics dynamic electrical characteristics bus (continued) high voltage rising output delay 200 r l 3332 , 1.0 s load time constants 4.0 s measured from txd=v il to v bus as follows: max time to v busmod = 3.7 v, 6.0 v v batt 26.5 v (12) min time to v busmod = 1.0 v, 6.0 v v batt 26.5 v (12) max time to v busmod = 9.4 v, 12.0 v v batt 26.5 v (12) t dlyhvro 2.0 2.0 2.0 ? ? ? 6.3 6.3 18 s high voltage falling output delay 200 r l 3332 , 1.0 s load time constants 4.0 s, 12.0 v v batt 26.5 v measured from txd=v ih to v bus as follows: max time to v busmod = 1.0 v (12) min time to v busmod = 3.7 v (12) t dlyhvfo 1.8 1.8 ? ? 14 14 s receiver rxd receive delay time (5.0 v v batt 26.5 v) awake t rdly 0.2 ? 1.0 s receive delay time (bus rising to rxd falling, 5.0 v v batt 26.5 v) sleep t rdlysl 10 ? 70 s cntl cntl falling delay time (5.0 v v batt 26.5 v) t cntlfdly 300 ? 1000 ms notes 12. v busmod is the voltage at the busmod node in figure 6 , page 13 . table 5. dynamic electrical characteristics (continued) characteristics noted under conditions of -40 c t a 125 c, unless otherwise stated. voltages are relative to gnd unless otherwise noted. all positive currents are into th e pin. all negative currents are out of the pin. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 33897 electrical characteristics timing diagrams timing diagrams figure 4. txd, bus and rxd waveforms in normal mode figure 5. txd, bus and rxd waveforms in high speed mode * v busmod is the voltage at the busmod node in figure 7 . txd bus rxd v il v ih v busmod t dlynormfo v nohf v bia v il v bia t rdly t dlynormro t rdly v ih v busmod * * * v bus is the voltage at the bus pin in figure 8 . txd bus rxd t dlyhsfo t dlyhsro v ih v il v bus * v bia v nohf t rdly v ih v bia v bus * v il t rdly
analog integrated circuit device data 12 freescale semiconductor 33897 functional description introduction functional description introduction the 33897 series is intended for use as a physical layer device in a single wire can communications bus. communications takes place from a single pin over a single wire using a common ground for a current return path. two data rates are available, with the high rate used for factory or assembly line communications and the lower for actual system communications where t he radiated emi of the higher rate could be an issue. two pins control the mode of operation (sleep, low speed, high speed, and high voltage wake-up). functional pin description the 33897 series is intended to be used with an mcu to control its operation and to pr ocess and generate the data for the bus. ground pins the four ground pins are not only for electrical conduction, their number and locations at each of the four corners serve also to remove heat from the ic. the biggest benefit of this is obtained by putting a lot of copper on the pcb in this area and, if ground is an internal layer, by adding numerous plated-through connections to it with the largest diameter holes the layout can use. txd data the data driven onto the swcan bus is inverted from the txd pin. a ?1? driven on txd will result in an undriven (recessive) state (bus at near ze ro volts). when the txd pin is low, the output goes to a driven state. the voltage and waveshaping in the driven stat e is determined by the levels on the mode0 and mode1 pins (refer to table 6 ). mode control the mode pins control the transmitter filtering and bus voltage and the ic sleep mode operation. table 6 shows the mode versus the logic levels on mode0 and mode1. the mode0 and mode1 pins have a weak pull-down in the ic so that in case the pi ns are not driven, the device will enter the sleep mode. this is usually the situation as the mcu comes out of reset, before the driving signals have been configured as outputs. rxd data the data received on the bus is translated to logic levels on this pin. this pin is a logic high when the bus is in the recessive state (near zero volt s) and is logic low when the bus is in either the normal or high voltage dominant state. this is an open-drain type of output that requires an external resistor to pull it up. when the device is in sleep mode, the output will be off unless a high voltage wake-up level is detected on the bus. if the wake-up level is detected, the output will be driven by the data on the bus. if the level of the data returns to normal level, the output will return to off after a short delay unless a non-sleep mode condition is set by the mcu. load switch this switch is on in all operating modes unless a loss of ground is detected. if this happens, the switch is opened and the resistor normally attached to its pin will no longer pass current to or from the bus. cntl output this logic level signal is used to control a v cc regulator. when the output is low, the v cc regulator is expected to shutdown. this is normally used to shut down the mcu and all the devices powered by v cc when the ic is in sleep mode. this is done to save power. when the part is taken out of the sleep mode by the higher than normal bus voltage, this pin is asserted high and the v cc regulator brings its output up to the regulated level. this starts t he mcu, which controls the mode of the ic. the mcu must change the mode signals to non- sleep mode levels in order to keep this pin from going low. there is a delay to allow the mcu to fully wake-up and take control after the high voltage signaling is removed before the level on this output returns low. after a delay time, even if the bus is at high voltage, the ic will return to sleep mode if both mode pins are low. table 6. mode control logic levels logic level operation mode0 mode1 0 0 sleep mode 0 1 high voltage wake-up mode 1 0 high speed mode 1 1 normal mode
analog integrated circuit device data freescale semiconductor 13 33897 functional description functional block diagram components vbatt input this power input is not reverse battery protected and should use an external diode to protect it from damage due to reverse battery if this protection is desired. the voltage drop of the diode must be take n into consideration when the operating range of the system is bei ng determined. this diode is generally used to protect the entire module from reverse battery and should be selected accordingly. bus i /o this input / output may require electrostatic discharge (esd) and /or emi external circuitry. a set of components is shown in the simplified application diagrams on page 15 . the value of the capacitor should be adjusted downward in direct proportion to the added capacitance of the esd or emi circuits. the series re sistance of the induct or should be kept below 3.5 to prevent its voltage drop from significantly degrading system noise margins. functional block diagram components timer osc this circuit generates a 500 khz signal to be used for internal logic. it is the reference for some of the required delays. timers this circuit contains the timing logic used to hold the cntl active for the required time after the conditions for sleep mode have been met. it is also used to keep the txd driver active for a period of time after it has generated a passive level on the bus. mode control this circuit contains the control logic for the various operating modes and conditions required for the ic. bus rcvr this circuit translates the levels on the bus pin to a cmos level indicating the presence of a logic [0] or a logic [1]. it also determines the presence of a high voltage wake-up (hvwu) signal that is passed to mode control and timers circuits. an analog filter is used to ?de-gl itch? the high voltage wake-up signal and prevent false ex its from the sleep mode. txd bus drvr this circuit drives the bus. it can drive it with the higher voltage wake-up signals when enabled by the mode control circuit. it can also provide waveshaping for reduced emi or not provide it for the higher data rate mode. the actual data is received on txd at cmos logi c levels, then translated by this circuit to the necessary operating voltages. under-voltage detect this circuit monitors internal operating voltage to assure proper operation of the part. if a low-voltage condition is detected, it sends a signal to disable the bus rcvr and txd bus drvr circuits. this prevents incorrect data from being put on the bus or sent to the mcu. load switch the load switch provides a pat h for an external resistor connected to the bus to be connected to ground. when a loss of ground is detected, this switch is opened to prevent the current that would normally be flowing to the ground from the module from going back thr ough the load resistor and raising the bus level. the circuit is opened when the voltage between gnd and vbatt become s too low as would be the case if module ground were lost. bus loading parameters figure 6. transmitter delays in normal and transmit high voltage wake-up modes 47 h 1.0 k c nom = 100 pf + (n -1) 220 pf r = 6.49 k (n -1) 33897 6.49 k bus load gnd 100 pf v batt note: the letter ?n? represents the number of nodes in the system. busmod
analog integrated circuit device data 14 freescale semiconductor 33897 functional description functional block diagram components figure 7. transmitter delays in transmit high speed mode 130 c nom = (n) 220 pf r = 6.49 k 33897 6.49 k bus load gnd (n -1) note: the letter ?n? represents the number of nodes in the system.
analog integrated circuit device data freescale semiconductor 15 33897 typical applications typical applications the 33897 can be used in applications where the module includes a regulator that has the capability of going into sleep mode by having an enable pin. see figure 8 . when the module?s regulator is in sleep mode, the module is turned off. the module waits for a defined wake-up voltage level on the bus. this wake-up voltage will activate the cntl line, which enables the regulator and turns the module back on. this feature allows the module to be more energy efficient since the current consumption is signifi cantly lowered when it goes into sleep mode. figure 8. 33897 typical application schematic gnd cntl vbatt load bus rxd mode0 txd voltage regulator 33897 en v cc mcu 10 k 2.7 k 6.49 k 1.0 k battery 47 h swc bus v cc power mode1 47 pf 100 pf source 4.7 f 4 100 nf
analog integrated circuit device data 16 freescale semiconductor 33897 packaging package dimensions packaging package dimensions important : for the most current package revision, visit www.freescale.com and perform a keyword search on the 98asb42565b drawing num ber below. dimensions shown ar e provided for re ference only. ef (pb-free) suffix 14-pin soicn 98asb42565b issue j
analog integrated circuit device data freescale semiconductor 17 33897 packaging package dimensions ef (pb-free) suffix 14-pin soicn 98asb42565b issue j
analog integrated circuit device data 18 freescale semiconductor 33897 revision history revision history revision date description of changes 9.0 5/2005 ? converted to freescale format ? added a & b versions ? updated device variation table, and note ?* recommended device for all new designs? ? added ef (pb-free) devices, and higher soldering temperature 10.0 8/2005 ? implemented revision history page ? updated simplified application diagrams ? updated typical application schematic 11.0 12/2005 ? added 33897c and d versions and timing diagrams 12.0 1/2006 ? updated table 4, static electrical c haracteristics - load and bus parameters ? updated ordering information. 13.0 6/2006 ? removed ?unless otherwise noted? from static el ectrical characteristic s & dynamic electrical characteristics table introductions 14.0 8/2006 ? added part numbers mc33897td and mc33897tef to ordering information on page 1. ? added 33897t to table 1, device variations on p age 3, referencing electrical changes per errata mc33897ter, revision 3 and specifying esd variations 15.0 10/2006 ? removed part numbers mc33897td/r2, mc33897tef/r2, mc33897clef/r2, pc33897clef/ r2, mc33897dlef/r2, and pc33897dlef/r2 ? added part numbers mcz33897ef/r2, mcz33897tef/r2, mcz33897aef/r2, mcz33897cef/ r2, mcz33897bef/r2, and mcz33897def/r2 to the ordering information block on page 1. ? updated device variations on page 2 for ?t? suffix products ? split out human body model on page 5 to differentiate between t and non-t versions ? added under-voltage hysteresis on page 6 ? removed peak package reflow temperature during reflow (solder reflow) parameter from maximum ratings on page 5 . added note with instructions to obtain this information from www.freescale.com . 16.0 6/2007 ? removed watermark, ?advance information? from page 1. 17.0 1/2011 ? improved hbm esd all pins except bus to 2.0 kv on mc33897ct ? added mc33897ctekf/r2 to the ordering information ? removed all 8-pin soicn device information ? changed short-circuit bus output current to -100 ma (approved by gm) 18.0 4/2012 ? updated quiescent current i qslp to 60 a max.
document number: mc33897 rev. 18.0 4/2012 information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fa bricate any integrated circuits on the information in this document. freescale reserves the right to make chang es without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particul ar purpose, nor does freescale assume any liability arising out of the application or us e of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in differ ent applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s te chnical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/freescale/docs/termsandconditions.htm freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c-ware, energy efficient solutions logo, mobilegt, powerquicc, qoriq, qorivva, starcore, and symphony are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, co renet, flexis, magniv, mxc, platform in a package, processor expert, qoriq qonverge, quicc engine, ready play, smartmos, turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support

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